1. Technical Field of the Invention
The present invention relates to a decoding circuit for receivers in mobile communication systems using code division multiple access (CDMA).
2. Description of the Prior Art
Conventional transmitters for spread spectrum (SS) communication under the CDMA modulate communication data are modulated beforehand by modulation techniques. In other words, the modulated communication data are further modulated by Pseudo Noise (PN) sequence for SS modulation in order to widen the transmission bandwidth. The widened transmission bandwidth is used for a plurality of channels, wherein different PN sequences are assigned for every user or every kind of information.
Therefore, receivers firstly despread the wide-band SS signal into its original bandwidth and then decodes the despread signal by using conventional techniques. Here, a correlation of PN sequence is detected between the received signal and the receiver side by despread filter such as a matched filter which handles the PN sequence as tap coefficients, or a adaptive filter which optimizes the despreading process by varying the tap coefficients.
The receiving side can pick up a communication signal among multiplexed communication signals by detecting the correlation. The picked-up signal is a complete auto-correlation of the desired signal, when the PN sequence of the receiving side has no cross-correlation with other PN sequences. However, in general, PN sequences have cross-correlation with each other. Therefore, the output from the despread filter contains interference signals which are not desired by the receiving side. The above-mentioned interference signals increase with the number of communication channels and degrade quality of received signal which is further degraded by thermal noise in the receiver and noises in transmission lines.
In the CDMA transmission, wherein information signal is spread by PN signal of which speed is higher than that of the information signal, prescribed pilot signals are inserted periodically in between the information signals, as shown in FIG. 8. Therefore, phase vectors of the information symbols are obtained by an interpolation on the basis of phase vectors of the pilot symbols, as shown in FIG. 9. Here, phase vector 1001 shows a track of end point of every symbol due to fluctuations in the transmission lines. Phase vector 1002 is a phase vector of every information symbol obtained by the interpolation. Phase vector 1003 is a phase vector which is an average phase vector in pilot symbol periods.
A decode circuit implementing the above-mentioned method is shown in FIG. 10. The decode circuit as shown in FIG. 10 comprises matched filter 803 which operates under chip cycle Tc with a tap length of 1 symbol, interpolation detection unit 807, and Decision unit 109.
The decode circuit as shown in FIG. 10 despreads SS signal 101, executes coherent detection, and outputs identified signal 102 on the basis of coherent detection.
Matched filter 803 comprises a plurality of delay units 804, a plurality of tap coefficient multipliers 805, and tap signal adder 806. Further, interpolation synchronous detector 807 for compensating a phase difference from matched filter 803 comprises amplitude phase estimation unit 105, first order interpolation unit 809, and coherent detection unit 108.
Amplitude phase estimation unit 105 pursues transmission estimation value 301 concerning the amplitude and phase in the transmission line, on the basis of a received phase of the pilot signal contained in the despread signal from matched filter 806.
First order interpolation unit 809 interpolates a received phase vector, inspecting a location of each information symbol.
Coherent detection unit 108 executes coherent detection, by compensating errors in the amplitude and phase of the information symbol on the basis of the received phase vector which is obtained by first order interpolation unit 809.
Decision unit 109 identifies a phase of the output from interpolation coherent detection unit 807. The output from Decision unit 109 is identified signal 102.
SS signal 101 as shown in FIG. 10 which contains known pilot symbol is inputted into matched filter 803 which has xe2x80x9cMxe2x80x9d taps extracted every chip cycle Tc. Here, an integer xe2x80x9cMxe2x80x9d is a spread factor. Signal vectors of each tap inputted into matched filter 803 are multiplied by tap coefficient vectors of which coefficient is determined by PN sequence. The tap coeflicient vector is CM, CMxe2x88x921, . . . , C2, Cl, as shown in FIG. 10. Then, the signals from each tap are added in tap signal adder 806 and outputted as a despread signal. Then, amplitude phase estimation unit 105 in interpolation coherent detection unit 807 pursues, by using the known pilot symbol, a received phase vector which represents errors of amplitude and phase due to the fluctuation of transmission lines. First order interpolation unit 809 interpolates a received phase vector, inspecting a location of each information symbol. Coherent detection unit 108 executes coherent detection, by compensating errors in the amplitude and phase of the information symbol on the basis of the received phase vector which is obtained by first order interpolation unit 809. Decision unit 109 identifies a phase of the output from interpolation coherent detection unit 807. The output from Decision unit 109 is identified signal 102.
The conventional decode circuit as shown in FIG. 10 compensates fading distortion by using the pilot signal.
However, when received SS signal contains the interference and noise which can not be neglected, the pilot signal is also distorted. Therefore, the coherent detection is not correctly executed, because the transmission lines can not be estimated correctly.
Therefore, the conventional decode circuit has a disadvantage that the coherent detection is not correctly executed, when the interference and noise can not be neglected.
Therefore, an object of the present invention is to provide a decode circuit with improved capability of coherent detection such that transmission lines are estimated correctly, even when the received SS signal contains much interference and noise.
A decode circuit of the present invention comprises a despreading filter for despreading spread spectrum (SS) signal, an amplitude phase estimation unit which estimates the amplitude and phase in transmission lines on the basis of pilot signals included in the despread signal, a reliability measurement unit for calculating a reliability value of the estimated amplitude and phase in the transmission lines, an interpolation unit for compensating the phase of information symbols by deciding a method of interpolation on the basis of the reliability, a coherent detection unit which detects the despread signal by using the interpolated estimation value in the transmission lines, and an decision unit for identifying the output from the coherent detection unit on the basis of its phase.
In short, the decode circuit of the present invention measures the reliability of the transmission line estimation value. Further, an interpolation method is decided on the basis of the reliability. Then, compensation vectors for compensating the phase are generated by the decided interpolation method to execute the coherent detection.
Therefore, the coherent detection is executed exactly, even when the interference and noise cannot be neglected.
Here, the reliability measurement unit may also calculate a reliability value of the detected signal outputted from the coherent detection unit.
According to the decode circuit of the coherent detection of the spread spectrum (SS) signal is optimized, even when the interference and noise can not be neglected.